Ferroelectric memory circuits have been proposed as a substitute for silicon memory circuits, such as dynamic random access memory (DRAM), static random access memory (SRAM), and electrically alterable read-only memory (EAROM). DRAM is the most inexpensive of these memories, but it needs to be refreshed every few milliseconds and is considered to be relatively slow. SRAM needs no refreshing as long as the power stays applied, and it is relatively fast, but it requires a large amount of power relative to DRAM. Furthermore, its memory states disappear if power is removed. EAROM has generally high access rates, and it is non-volatile upon the removal of power, but its writing time is slow and the number of writing cycles is generally limited. Furthermore, it does not form in dense integrated circuits.
Ferroelectric memory (FRAM) offers the promise of overcoming the limitations stated above. FRAM is based on the same fundamental storage concept as DRAM, a storage capacitor in which is stored or not stored a charge representing a memory state. However, in a FRAM the capacitor core includes a ferroelectric material that is can be electrically poled into either of two stable polarization states. Once poled into one of these states, the ferroelectric capacitor remains in that state even if power is removed, and its charge state can be read after the FRAM is subsequently powered up. As a result, it provides the non-volatile storage representative of EAROM. However, it can generally be read and written at speeds representative of DRAM and SRAM. It offers much lower power consumption than DRAM or SRAM because no powering or refreshing is required for storage. Furthermore, the high charge storage available in the ferroelectric material of dielectric constant and the resemblance to DRAM means that FRAM memories can be integrated to very high densities. Yet further, the high charge storage increases the cell's resistance to various types of radiation effects.
However, if FRAM it to be commercially viable, it must be integrated on silicon substrates, either so that the silicon provides support functions such as read, write, and gating circuitry for large-scale FRAM or so that the FRAM serves as auxiliary memory for silicon logic. The integration of ferroelectrics with silicon has proven difficult. Two principal problems have been the diffusion of oxygen from the ferroelectric cell into the underlying silicon substrate and the deleterious effects upon the ferroelectric of the hydrogen anneal usually required for silicon integrated circuits.
Ferroelectrics are almost invariably based upon highly oxidized metal crystals or polycrystals such as PbTi.sub.1-x Zr.sub.x O.sub.3 (PZT). PZT has a simple lattice structure represented in the crystalline unit cell representation in FIG. 1, which is a tetragonal unit cell having equal a and b axes and a slightly larger c axis so that the cell is approximately cubic. The lead (Pb) atoms 10 having a charge state of +2 occupy the corners of the tetragonal cell, the oxygen (O) atoms 12 having a charge state of -2 occupy the faces of the cell, and the titanium (Ti) or zirconium (Zr) atom having a charge state of +4 occupies approximately the cell center. Above the Curie temperature (T.sub.c), the cell is cubic (a=b=c), but below the Curie temperature the cell assumes the somewhat non-cubic structure of FIG. 1. The Ti or Zr atom does not occupy the exact center of the cell but instead can occupy one of two equivalent positions 14a, 14b slightly above or below the center along the c-axis. Both of these states are stable under operational conditions and represent the two polarization states of the Ti and Zr cations relative to the O anions. Other ferroelectrics have different and possibly more complex structures, but most have a structure sharing chemical effects with those of PZT.
A thin layer of a ferroelectric material such as PZT is typically deposited or at least annealed in a high-temperature, oxygen-rich ambient. Usually, the temperature is above the Curie temperature, which for PZT is about 390.degree. C. For silicon integration, the ferroelectric layer is deposited and processed after the silicon level has been processed. Such high-temperature processing in an oxygen environment is considered to be disadvantageous if not fatal for a silicon circuit.
In the older, conventional techniques for fabricating ferroelectric cells, the ferroelectric layer is deposited by sol-gel or other processes which produce a randomly oriented polycrystalline ferroelectric layer. This crystalline structure has the disadvantage of large inter-granular boundaries along which oxygen can propagate from the oxygen-rich ferroelectric to the underlying silicon, at the boundary of which the oxygen and silicon reactor to form silicon dioxide, producing a strongly electrically insulative layer. Platinum (Pt) has long been proposed as an interfacial barrier between the ferroelectric and the underlying silicon. Although platinum is a relatively noble material, it has been found to be a poor barrier for oxygen migration from the ferroelectric to the underlying silicon.
Ramesh and his group have disclosed in various patents and publications (see, for example, U.S. Pat. No. 5,798,903) the technique of avoiding the problems associated with polycrystalline ferroelectrics by epitaxially growing a crystallographically oriented ferroelectric layer on a metal-oxide layer, which also acts as an electrode. The metal-oxide layer either itself provides a crystallographically templating function or is epitaxially grown on another crystallographically templating layer. A templating layer self-aligns to a thermodynamically preferred crystalline orientation, even when grown on an unaligned substrate, and thereafter serves as a crystallographic template for epitaxial growth of over layers. The early templating layers were the layered (distinctly non-cubic) perovskites, but cubic perovskites, such as lanthanum strontium cobalate (LSCO) have been shown to effectively template after grown perovskite layers. The crystallographically oriented ferroelectric layer reduces the area of inter-granular boundaries, thus reducing the amount of oxygen diffusion from the growing ferroelectric to the underlying silicon. Furthermore, Dhote and Ramesh in U.S. Pat. No. 5,777,356, incorporated herein by reference in its entirety, have disclosed the use of an effective barrier to oxygen diffusion placed between the lower metal oxide electrode and the silicon, specifically an intermetallic metal such as Ti.sub.3 Al, although many other compositions are possible.
A ferroelectric random access memory (FRAM) cell 20 is illustrated in the cross-sectional view of FIG. 2. Many such memory cells are formed in an integrated circuit memory together with silicon-based support circuitry on a &lt;001&gt;-oriented crystalline silicon substrate 22. Each cell includes both a ferroelectric capacitor and a silicon transistor gating the ferroelectric capacitor to read and write lines. The metal-oxide-semiconductor (MOS) transistor is created in part by forming source and drain wells 24, 26 having a conductivity type opposite to that of the substrate 22. The intervening gate region is overlaid with a gate structure 28 including an unillustrated thin gate oxide facing the silicon gate region G and an unillustrated upper metal gate line, for example of aluminum, to control the gate.
A first inter-level dielectric layer 30 is deposited over the substrate and the transistor structure. A through hole 32 is etched through the first inter-level dielectric layer 30 in the area over the source well 24, and polysilicon is filled into the through hole 32 to form a polysilicon contact plug to the transistor source. A metal source line 34 is photolithographically delineated on top of the first inter-level dielectric layer 30 and electrically contacts the polysilicon plug 32.
A second inter-level dielectric layer 36 is then deposited over the first inter-level dielectric layer 30. Another through hole 38 is etched through both the first and second inter-level dielectric layers 30, 36 over the area of the drain well 26, and polysilicon is filled into the second through hole 38 to form a contact plug to the transistor drain.
A lower ferroelectric stack is then deposited and defined over the polysilicon plug 38. It includes a polysilicon layer 40 to promote electrical contact to the polysilicon plug 38, a titanium nitride (TiN) layer 42 acting as a first conductive barrier between the underlying polysilicon 40 and the oxidizing ferroelectric layer and its oxide electrodes, an intermetallic layer 44 acting as the primary barrier, and a lower metal-oxide electrode 46.
Growth of the metal-oxide electrodes 46, 52 and the ferroelectric layer 50 is performed at temperatures in the range of 500.degree. to 650.degree. C., the highest temperatures achieved in the processing after the deposition of the intermetallic layer 44.
A field-oxide layer 48 is formed around the sides of the lower ferroelectric stack and extends over its rim and laterally outwards from its bottom but leaves a central aperture for the after deposited upper ferroelectric stack.
The upper ferroelectric stack is then deposited and defined to fill the aperture in the field oxide layer 48 but not to extend beyond the end of its foot. The upper ferroelectric stack includes the ferroelectric layer 50, the upper metal-oxide electrode layer 52, and a platinum layer 54. Although the illustrated ferrolectric layer has a composition of lead niobium zirconium titanate (PNZT), the following discussion will use the simpler lead zirconium titanate (PbZr.sub.x Ti.sub.1-x O.sub.3 or PZT). The upper and lower metal oxide electrodes 46, 52 are preferably formed of lanthanum strontium cobalate (LSCO) of the approximate composition LaSr.sub.0.5 Co.sub.0.5 O.sub.3. LSCO not only acts as a conductive metal oxide electrode, but it also provides a fairly strong crystallographic templating function.
A third inter-layer dielectric layer 56 is deposited around the upper and lower ferroelectric stacks. A via hole 60 is etched down to the platinum layer 54, and Ti/W is filled into the hole to form a via 60 contacting the platinum layer 54. An aluminum layer is deposited and delineated to form an interconnect line 62 connected to the via 60.
Although the structure shown in FIG. 2 offers many operational advantages, it has been difficult to integrate the ferroelectric structure with conventional silicon circuitry. It has long been known in silicon processing that dangling oxygen bonds tend to form at the interface between the silicon substrate 22 and overlying silicon oxide, such as in the field oxide 30 and the gate oxide in the transistor gate structure 28. Such dangling bonds tend to accumulate charge and shift the transistor threshold voltages, rendering the transistor leaky, hard to control, and at worst inoperable. However, it has also long been long known that the interfacial bonds can be tied up by an anneal in a hydrogen environment in the vicinity of 200 to 400.degree. C. after the formation of the oxide/silicon interface. A typical annealing ambient is 4% hydrogen in nitrogen. It is believed that the very mobile hydrogen atoms quickly diffuse through the overlying oxide and bond with the free oxygen bonds. This anneal is often referred to as a forming-gas anneal although hydrogen in a nitrogen carrier is the predominant forming gas used. The forming-gas anneal also reduces the level of defects in the material, such as may result from ion implantation of the source and drain.
The integrated ferroelectric memory structure of FIG. 2 also needs to be subjected to a forming-gas treatment because of the active silicon circuitry overlaid by the oxide layer 30. However, in this structure the platinum electrode acts as a catalyst to reduce molecular hydrogen H.sub.2 to atomic hydrogen H, which is thus freely available in the upper area of the ferroelectric capacitor, and atomic hydrogen is extremely mobile.
It is known that the perovskite ferroelectric layer and the metal-oxide electrode layers are best deposited in a highly oxidizing environment at temperatures between about 500 and 650.degree. C. In the parent application, incorporated herein by reference in its entirety, Aggarwal et al. disclose the advantage of a post-deposition rapid thermal anneal (RTA) at 750.degree. C., which is performed in an air or oxygen ambient. If the silicon circuitry experiences these temperatures, particularly in an oxygen-rich ambient, after the forming-gas anneal, whatever hydrogen has bonded at the oxide/silicon is likely to debond and diffuse back out of the wafer. Therefore, it seems inevitable that the forming-gas anneal be performed after the perovskite deposition and RTA. That is, the ferroelectric stack will be exposed to the forming-gas anneal.
However, ferroelectric capacitors react poorly to the forming-gas anneal and tend to lose their hysteretic characteristics required for ferroelectric memory. Furthermore, the damage seems to be accelerated with the upper platinum electrode in the more conventional Pt/PZT/Pt ferroelectric stack. See, for example: (1) Kushida-Abdelghafar et al., "Electrode-induced degradation of Pb(Zr.sub.x Ti.sub.1-x)O.sub.3 (PZT) polarization hysteresis characteristics in Pt/PZT/Pt ferroelectric thin-film capacitors," Applied Physics Letters, vol. 69, no. 21, 1996, pp. 3188-3190; (2) Shimamoto et al., "H.sub.2 damage of ferroelectric Pb(Zr, Ti)O.sub.3 thin-film capacitors--The role of catalytic and adsorptive activity of the top electrode," Applied Physics Letters, vol. 70, no. 23, 1997, pp. 3096, 3097; and (3) Han et al., "Electrode dependence of hydrogen-induced degradation in ferroelectric Pb(Zr,Ti)O.sub.3 and SrBi.sub.2 Ta.sub.2 O.sub.9 thin films," Applied Physics Letters, vol. 71, no. 9, 1997, pp. 1267-1269. These articles associate the hydrogen-induced ferroelectric degradation with the platinum top electrode catalyzing molecular hydrogen to produce atomic hydrogen, which then reduces PZT at the PZT/Pt interface, thereby removing oxygen from the oxide ferroelectric. Shimamoto et al. suggest using instead a top electrode of gold or silver. Han et al. seem to suggest recovering the forming-gas damage with a 450.degree. C. recovery anneal in oxygen. However, they do not address the effect of the recovery anneal on characteristics of the oxide/silicon interface, the reason for the forming-gas anneal.
Accordingly, it is greatly desired to provide the integration of ferroelectric capacitors with silicon integrated circuits. In particular, it is desired to provide either a method or a structure that prevents the damage of ferroelectric effects by a forming-gas anneal.